IDT82V3202NLG【PDF 35/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

3.6.2

FORCED SELECTION

In Forced selection, the selected input clock is set by the

T0_INPUT_SEL[3:0] bits. The results of input clocks quality monitoring

(refer to Chapter 3.5 Input Clock Quality Monitoring) do not affect the

input clock selection.

3.6.3

AUTOMATIC SELECTION

In Automatic selection, the input clock selection is determined by its

validity and priority. The validity depends on the results of input clock

quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).

In the qualified input clocks, the one with the higher priority is selected.

The

priority

configured

the

corresponding

INn_CMOS_SEL_PRIORITY[3:0] bits (n = 1 or 2). If more than one

qualified input clock is available and has the same priority, the input

clock with the smaller ‘n’ is selected. See Table 8 for the ‘n’ assigned to

the input clock.

Table 8: ‘n’ Assigned to the Input Clock

Input Clock

‘n’ Assigned to the Input Clock

IN1_CMOS

IN2_CMOS

Table 9: Related Bit / Register in Chapter 3.6

Bit

Register

Address (Hex)

EXT_SW

MON_SW_PBO_CNFG

T0_INPUT_SEL[3:0]

T0_INPUT_SEL_CNFG

INn_CMOS_SEL_PRIORITY[3:0] (n = 1 or 2)

IN1_IN2_CMOS_SEL_PRIORITY_CNFG

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